1. Field of the Invention
This invention relates generally to power management within computer systems and, more particularly, to a system and method for turning on and off a peripheral bus clock signal through a bus bridge or peripheral devices to conserve power. Still more particularly, the present invention relates to a system and method for enabling or disabling this power saving feature based upon whether the bus bridge and peripheral devices are capable of supporting this feature.
2. Description of the Relevant Art
An ongoing developmental goal of manufacturers has been to reduce the power consumption of computer systems. Reducing power consumption typically reduces heat generation of the system, thereby increasing reliability and decreasing cost. In addition, power reduction has been particularly important in maximizing the operating life of battery-powered portable computer systems.
Various techniques have been devised for reducing the power consumption of computer systems. These techniques include increasing the integration of circuitry and incorporation of improved circuitry and power management units (PMU's). One specific technique involves the capability of stopping clock signals that drive inactive or idle circuit portions. A system employing such a technique typically includes a power management unit that detects or predicts inactive circuit portions and accordingly stops the clock signals that are associated with the inactive circuit portions. By turning off "unused" clock signals, overall power consumption of the system is decreased.
Although the capability of stopping "unused" clock signals has been generally successful in reducing power consumption, the technique has generally not been applied to clock signals that drive peripheral buses having alternate bus masters connected thereto. The reason for this limitation is best understood from the following example.
FIG. 1 is a block diagram that illustrates a computer system 10 including a microprocessor (CPU) 12, a system memory 14, a bridge/memory controller 16, and a bus interface and arbiter unit 18. A CPU local bus 20 couples the microprocessor 12 to bridge/memory controller 16 and bus interface and arbiter unit 18. A system memory bus 22 couples system memory 14 to bridge/memory controller 16. An alternate bus master 26 labeled "Master1" and a second alternate bus master 28 labeled "Master2" are coupled to the bus interface and arbiter unit 18 through a peripheral bus 30. A slave device 31 is similarly coupled to bus interface and arbiter unit 18 through peripheral bus 30.
When alternate bus master 26 requires mastership of peripheral bus 30, a request signal labeled REQ1 is asserted by the alternate bus master 26 and is detected by bus interface and arbiter unit 18. If mastership of the bus is granted in accordance with the internal arbitration logic, the bus interface and arbiter unit 18 asserts a grant signal labeled GNT1 and, accordingly, alternate bus master 26 attains mastership of peripheral bus 30 and may execute the desired cycle.
In the system of FIG. 1, the request signal REQx (i.e., REQ1 or REQ2 must be asserted by the associated alternate bus master synchronous to the peripheral bus clock signal CLK. This requirement is specified by several prevalently utilized peripheral bus standards, such as the PCI bus standard. As a result of this requirement, systems employing such peripheral bus standards are designed such that the peripheral bus clock signal CLK is always turned on, thereby allowing an alternate bus master to generate a synchronous request signal. In such systems, however, power is wasted when the peripheral bus is idle.
An additional hindrance to the employment of clock-stopping power reduction techniques for peripheral buses arises since slave devices may require a clock signal beyond the end of a peripheral bus cycle. For example, additional clock cycles may be required at the completion of a peripheral bus cycle for slave device 31 to empty an internal FIFO. If the clock signal were stopped during such a situation, the performance of the system as well as the integrity of data may be adversely affected.
The assignee of the present invention recently has overcome the problems inherent in stopping a bus clock signal and has developed a system to control a peripheral bus clock signal, which is disclosed in commonly assigned U.S. application Ser. No. 08/131,092, filed Oct. 1, 1993, the teachings of which are incorporated by reference as if fully set forth herein. The system disclosed in that application makes it possible to turn on and turn off a peripheral bus clock (such as a PCI bus), based upon usage of that bus by the central processing unit or other peripheral devices located on the peripheral bus. This power saving feature is referred to herein as the "clock run" function or feature.
One potential drawback to implementing the clock run feature, however, is that some of the components on the peripheral bus may not be capable of supporting this feature. The use of the system in such an instance will result in system errors and/or will result in certain components being unable to operate when the bus clock signal is deactivated. For example, if a peripheral master is included on the peripheral bus that does not have the capability of requesting the peripheral bus clock signal to restart during periods when the clock is stopped, this peripheral master may be rendered inoperable during these periods of clock deactivation.
It would be desirable therefore to develop a system in which the system automatically determines if the power-saving clock run feature disclosed in commonly assigned U.S. application Ser. No. 08/131,092 can be implemented based upon the capabilities of the components located on the peripheral bus.